Multiple-value resistor network

ABSTRACT

A method and apparatus provides resistor networks with two or more resistance values, which may accommodate different circuit configurations with a common circuit assembly. Also, the present invention provides a packaging method using multiple-value resistor networks as connecting and disconnecting mechanisms for the signal lines on the package.

BACKGROUND OF THE INVENTION

[0001] This invention relates to resistor elements and resistornetworks.

[0002] Electronic circuit modules sometimes contain resistor networks toincorporate multiple resistors of the same value.

[0003] A 64-bit memory module normally contains 16 resistor networks,each with 4 resistor elements with a value of 10 ohms.

[0004] In order to construct usable memory module packages withpartially defective memory chips, the on-board resistors are required tohave certain combinations of values.

[0005] Using 64 or 128 single individual resistors is certainly one wayto accommodate this situation. However, the assembly process is moretime consuming. It is also subject to certain limitation on the totalnumber of onboard components.

[0006] Using different printed circuit boards for differentconfigurations is another way to cope with the situation. However, theinventory and production control becomes quite complex.

BRIEF SUMMARY OF THE INVENTION

[0007] This invention proposes a method and apparatus to generateresistor networks with multiple values.

[0008] This invention provides a method to accommodate differentcomponent configurations with a single printed-circuit board.

[0009] This invention further provides a method to simplify themanufacturing process of an electronic circuit module.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a diagram of a prior art resistor network.

[0011]FIG. 2 is a diagram of a prior art memory circuit block.

[0012]FIG. 3 is a diagram of a prior art memory module.

[0013]FIG. 4 shows a number of preferred embodiments of the presentinvention for a multiple-value resistor network.

[0014]FIG. 5 shows a preferred embodiment of the present invention for amemory circuit block.

[0015]FIG. 6 shows a preferred embodiment of the present invention for amemory module.

DETAILED DESCRIPTION OF THE INVENTION

[0016] The present invention will be illustrated with some preferredembodiments.

[0017]FIG. 1 is a diagram of a prior art resistor network. The resistornetwork 101 contains resistors 102, 103, 104, and 105. All fourresistors are of the same value, for example, 10 ohms.

[0018]FIG. 2 is a diagram of a prior art memory circuit block. Thememory circuit block 201 consists of a memory chip 202 and a resistorgroup 203. The resistor group contains two resistor networks 204 and205.

[0019] Each resistor network contains 4 resistor elements of the samevalue, 10 ohms. A resistor element serves as a connecting mechanism tolink a data bit line 206 on the memory chip to a data bit line 207 onthe memory circuit block.

[0020]FIG. 3 is a diagram of a prior art memory module. The memorymodule 301 contains eight memory circuit blocks 302. A memory circuitblock 302 consists of a memory chip 303 and a resistor group 304.

[0021] The resistors serve as connecting mechanisms to link the data bitlines on the memory chips to the data bit lines on the memory circuitblocks. The data bit lines on the memory circuit blocks are connected tothe edge connector 305 of the memory module.

[0022]FIG. 4 shows a number of preferred embodiments of the presentinvention for a multiple-value resistor network.

[0023] The resistor network 401 contains resistors 411, 412, 413, and414. The resistors 411, 412, and 413 are of one value, for example 10ohms. The shaded resistor 414 has a different value, for example, 1 megaohms.

[0024]FIG. 4 shows eight different combinations of multiple-valueresistor networks with two different values. Shaded resistors are with aresistance value of 1 mega ohms. Blank resistors are with a resistancevalue of 10 ohms.

[0025] There are a total of 16 ways to combine four resistors with twopossible values. Besides the eight combinations 401, 402, 403, 404, 405,406, 407, and 408 shown in FIG. 4, six more combinations may be obtainedby turning resistor networks 401, 402, 403, 404, 407, and 408 clockwise180 degrees. The remaining two combinations contain only one resistancevalue, either 10 ohms or 1 mega ohms.

[0026]FIG. 5 shows a preferred embodiment of the present invention for amemory circuit block. The memory circuit block 501 consists of twomemory chips 502, 503, and a resistor group 504. The resistor groupcontains four resistor networks, each with 4 resistors.

[0027] The resistors 510, 511, 512, 513, 514, 515, 516, and 517 link thedata bit lines on the memory chip 502 to the memory bit lines 530, 531,532, 533, 534, 535, 536, and 537 on the memory circuit block.

[0028] The resistors 520, 521, 522, 523, 524, 525, 526, and 527 link thedata bit lines on the memory chip 503 to the memory bit lines 530, 531,532, 533, 534, 535, 536, and 537 on the memory circuit block.

[0029] In memory chip 502, memory bit positions D1, D3, D4, D6, and D7are marked as defective because they contain at least one defectivememory blocks. The remaining bits D0, D2, and D5 contains onlyfunctional memory blocks.

[0030] Resistors 510, 512, and 515 with a low resistance value serve asconnecting mechanisms to link the functional data bits D0, D2, and D5 tothe data lines 530, 532, and 535 of the circuit block. Resistors 511,513, 514, 516, and 517 with a high resistance value serve asdisconnecting mechanisms to block D1, D3, D4, D6, and D7 from thecircuit block data lines.

[0031] In memory chip 503, memory bit positions D0, D2, D5 are marked asdefective because they contain at least one defective memory blocks. Theremaining bits D1, D3, D4, D6, and D7 contains only functional blocks.

[0032] Resistors 521, 523, 524, 526, and 527 with a low resistance valueserve as connecting mechanisms to link the functional data bits D1, D3,D4, D6, and D7 to the data line 531, 533, 534, 536 and 537 of thecircuit block. Resistors 520, 522, and 525 with a high resistance valueserve as disconnecting mechanisms to block D0, D2, D5 from the circuitblock data lines.

[0033]FIG. 6 shows a preferred embodiment of the present invention for amemory module. The memory module 601 contains eight memory circuitblocks 602. A memory circuit block 602 consists of two memory chips 603,604, and a resistor group 605.

[0034] The resistors serve either as connecting mechanisms to link thefunctional chip data bit lines to the circuit block data bit lines or asdisconnecting mechanisms to block the defective chip data bit lines fromthe circuit block data bit lines.

[0035] The data bit lines on the memory circuit blocks are connected tothe edge connector 606 of the memory module.

I claim:
 1. A resistor network package comprising: (a) a plurality ofexternal contact points; (b) a plurality of first sub-packages each witha first resistance value between two external contact points; (c) aplurality of second sub-packages each with a second resistance valuebetween two external contact points; wherein said first resistance valueis different from said second resistance value; wherein the differencebetween said first resistance value and said second resistance value islarger than 50% of the first resistance value.
 2. The resistor networkpackage of claim 1 wherein said first sub-package is a low-impedancematerial, a low-value resistor, a zero-ohm resistor, or a close-circuitconnection.
 3. The resistor network package of claim 1 wherein saidsecond sub-package is a high-impedance material, a high-value resistoror an open-circuit condition.
 4. An electronic circuit assemblycomprising: (a) a plurality of resistor network packages, at least oneof which contains a first sub-package with a first resistance valuebetween two external contact points and a second sub-package with asecond resistance value between two external contact points, said secondresistance value is different from the first resistance value by atleast 50% of the first resistance value. (b) a plurality of assemblysignal lines; (c) a circuit sub-assembly having a plurality ofsub-assembly signal lines; wherein at least one said sub-package in aresistor network package links one said sub-assembly signal line to onesaid assembly signal line.
 5. The electronic circuit assembly of claim 4wherein said first sub-package is a low-impedance material, a low-valueresistor, a zero-ohm resistor, or a close-circuit connection.
 6. Theelectronic circuit assembly of claim 4 wherein said second sub-packageis a high-impedance material, a high-value resistor or an open-circuitcondition.
 7. An electronic circuit assembly comprising: (a) a pluralityof resistor network packages, at least one of which contains a firstsub-package with a first resistance value between two external contactpoints and a second sub-package with a second resistance value betweentwo external contact points, said second resistance value is differentfrom the first resistance value by at least 50% of the first resistancevalue. (b) a plurality of assembly signal lines; (c) a first circuitsub-assembly having a plurality of first sub-assembly signal lines; (d)a second circuit sub-assembly having a plurality of second sub-assemblysignal lines; wherein at least a first sub-package in a resistor networkpackage links one said first sub-assembly signal line to a first saidassembly signal line. wherein at least a second sub-package in aresistor network package links one said second sub-assembly signal lineto a second said assembly signal line.
 8. The electronic circuitassembly of claim 7 wherein said first sub-package is a low-impedancematerial, a low-value resistor, a zero-ohm resistor, or a close-circuitconnection.
 9. The electronic circuit assembly of claim 7 wherein saidsecond sub-package is a high-impedance material, a high-value resistoror an open-circuit condition.